2025·Hardware methodology engineer
RTL Connectivity & Clock/Reset Automation Tool
C++17 tool that parses hardware module specs and auto-generates Verilog top-level wrappers with validated connectivity and automated clock/reset insertion.
Stack
C++17,Verilog RTL,Python,CMake,Make,GoogleTest,Verilator
Timeline
2025
Impact
- YAML/JSON spec → auto-generated Verilog top-level wrappers
- Graph-based connectivity validation via topological traversal
- Automated clock/reset insertion + reset synchronizer generation
Context & Goals
Built an RTL generation tool that turns declarative hardware module specs into correct-by-construction Verilog top-level wrappers — modeled on ASIC/hardware methodology workflows (aligned with the NVIDIA Clocks team's domain). The goal: remove the manual, error-prone wiring of clocks, resets, and module interconnects.
Architecture
- Spec parsing: ingests module definitions from YAML/JSON and builds an in-memory connectivity model.
- Connectivity validation: represents the design as a graph and runs topological traversal to detect cycles, dangling ports, and width/direction mismatches before any RTL is emitted.
- Clock/reset automation: inserts clock and reset trees automatically and generates reset synchronizers to avoid metastability across clock domains.
- Verilog emission: produces clean, lint-friendly top-level
.vwrappers.
Highlights
- Integrated Verilator linting into the generation pipeline so emitted RTL is checked on every build.
- Unit-tested the parser, graph engine, and emitter with GoogleTest; build orchestrated with CMake/Make.
- Designed the spec format to be diff-friendly so connectivity changes are reviewable in version control.
What I'd do next
- Publish sample generated
.vfiles alongside the generator for quick evaluation. - Add SDC constraint generation and CDC report export.